Files
MeshCoreTel-firmware/arch
Valentin V. Bartenev 72fc497980 Slightly optimize CPU util tracking by branchless tick hook
Replace the two separate volatile counters (s_idle_ticks, s_busy_ticks)
with a two-element array s_ticks[2]:

  [0] = idle ticks   (xTaskGetCurrentTaskHandle() != s_idle_handle → false → 0)
  [1] = busy ticks   (xTaskGetCurrentTaskHandle() != s_idle_handle → true  → 1)

The tick hook becomes a single branchless statement:

  s_ticks[xTaskGetCurrentTaskHandle() != s_idle_handle]++;

This eliminates the conditional branch from the tick ISR at the cost
of a few additional instructions in IRAM.  On Xtensa LX7 the branch
is somewhat unpredictable — the system alternates between idle and
busy — so removing the misprediction penalty (~5–10 cycles/call)
outweighs the slightly larger code size.

_onSample() is updated to read s_ticks[0] (idle) and s_ticks[1]
(busy) accordingly. All other logic is unchanged.
2026-05-10 10:02:21 +03:00
..
2025-05-11 09:28:15 +02:00